1. Technical Field:
The present invention is directed to an improved data processing system and in particular to an improved data cache array for utilization in a data processing system. Still more particularly the present invention relates to an improved method and system for efficient miss sequence cache line allocation.
2. Description of the Related Art:
Many systems for processing information include both a system memory and a cache memory. A cache memory Is a relatively small, high-speed memory that stores a copy of information from one or more portions of the system memory. Frequently, the cache memory is physically distinct from the system memory. Such a cache memory can be integral with the processor device of the system or non-integral with the processor.
Information may be copied from a portion of the system memory into the cache memory. The information in the cache memory may then be modified. Further, modified information from the cache memory can then be copied back to a portion of the system memory. Accordingly, it is important to map information in the cache memory relative to its location within system memory.
Attempted access of data within the cache memory often achieves a success rate of greater than ninety percent; however, if the attempted access of data is unsuccessful, the desired data must be located within system memory and written into the cache memory. While this process is relatively straightforward, the decision of what data to delete from the cache in order to write the desired data into the cache is non-trivial in nature.
Prior art cache systems often utilize a separate tracking array which implements a "Least Recently Utilized" algorithm along with data validity indications so that the decision to replace a selected line of information may be made intelligently. While this technique works relatively well it involves an increase in bus routing and the number of cycles required to allocate a block of information for replacement within an associated cache.
Thus, it should be seen that a need exists for an improved method and system for efficient miss sequence cache line allocation wherein the replacement of blocks of information within a cache may be more efficiently accomplished.